1. Field of the Invention
The present invention relates to a semiconductor device, a photomask and a manufacturing method of a semiconductor device. More specifically, the present invention relates to a semiconductor device, a photomask and a manufacturing method of a semiconductor device enabling easier measurement of a registration mark and the like in the manufacturing steps.
2. Description of the Background Art
Conventionally, various process steps including film formation and photolithography have been taken in manufacturing a semiconductor device. In the step of exposure during photolithography, a mask pattern formed on a photomask is projected on a photoresist film or the like on a semiconductor substrate, using an exposure apparatus that is called a stepper. As a method used in the step of exposure, the step-and-repeat method has been known, in which the semiconductor substrate is fixed on a two-dimensionally movable X-Y stage, and the step of exposure is conducted every time the semiconductor substrate is moved by a prescribed distance.
FIG. 37 is a schematic plan view showing a conventional photomask used in the above described step of exposure. The photomask will be described with reference to FIG. 37.
Referring to FIG. 37, a photomask 120 has a transfer pattern formed using a metal film or the like which intercepts exposure light beam, on a substrate which transmits the exposure light beam. Photomask 120 shown in FIG. 37 includes a chip area 111 in which a transfer pattern of a semiconductor element, for example, is formed, and dicing areas 153, 154, 161 to 163 arranged surrounding the chip area 111 for forming a dicing line area. Mask patterns 121 to 127 for forming inspection marks are formed in dicing areas 153, 154, 161.
In photomask 120 shown in FIG. 37, it is necessary to make as small as possible the width of dicing areas 153, 154 and 161 to 163, and to arrange mask patterns 121 to 124 to form inspection mark areas 129a to 132a (see FIG. 38) such as the registration marks, at least at four corners of photomask 120. For this purpose, a so called projected and recessed dicing structure is employed. More specifically, a light shielding member 110 such as a chromium film is arranged at a prescribed area, so that a first outer peripheral dicing area 153 allowing passage of exposure light comes to have a projected portion 155 having relatively wide width and recessed portions 156 and 157 having relatively narrow widths. In the second outer peripheral dicing area 154, a light shielding member 110 is so arranged as to form a recessed portion 158 and projected portions 159 and 160, which fit the projected portion 155 and recessed portions 156 and 157 of the first outer peripheral dicing area 153. When circuit patterns are transferred on the semiconductor substrate by the step-and-repeat method using such a photomask 120, the structure shown in FIG. 38 results.
FIG. 38 is a schematic view of the structure obtained when the transfer patterns are transferred to the main surface of the semiconductor substrate using photomask 120 shown in FIG. 37. The chip area 128a and inspection mark areas 129a to 135a are simultaneously transferred by one step of exposure (one shot). The chip area 128b and inspection mark areas 129b and 132b are transferred by one shot, and the chip area 128c and inspection mark areas 130c and 131c are transferred by one shot, respectively.
In this manner, when photomask 120 shown in FIG. 37 is used, it is possible to set the width of dicing line area 113 to be approximately the same as the width of inspection mark areas 129a to 135a, 129b, 130c, 131c and 132b, and it is also possible to arrange inspection marks 129a to 132a at four corners of the area transferred by one step of exposure.
FIG. 39 is a schematic plan view showing the conventional registration mark 115 formed in inspection mark areas 129a to 135a, 129b, 130c, 131c and 132b shown in FIG. 38. FIGS. 40 and 41 are schematic cross sections of FIG. 39 taken along the lines XL—XL and XLI—XLI, respectively. The registration mark 115 will be described with reference to FIGS. 39 to 41.
Referring to FIGS. 39 to 41, the registration mark 115 is used to confirm registration accuracy of patterns in the step of exposure between a layer including trench isolation insulating films 101 and 101b as the lower layer to be registered and the layer including a first interconnection 103b as an upper layer to be registered. The trench isolation insulating film as the lower layer forms a first registration inspection pattern 101a. The first inspection pattern 101a has a rectangular planar shape. In an area positioned inside the first inspection pattern 101a, a second inspection pattern 103a having a rectangular planar shape is formed by the first interconnection as the upper layer to be registered. By measuring positional relation (such as the distance in horizontal direction) between the first and second inspection patterns 101a and 103a, it is possible to measure registration accuracy of the circuit pattern transferred in the step of exposure to form trench isolation insulating film 101 and the circuit pattern transferred in the step of exposure to form the first interconnection 103b. 
In registration mark 115, a trench isolation pattern identification (ID) sign 116 identifying the step of exposure to form the lower layer including trench isolation insulating film 101 is formed by trench isolation insulating film 101b. Further, a first interconnection pattern identification (ID) sign 117 for identifying the step of exposure to form the upper layer including the first interconnection 103b is formed by the first interconnection 103b. As the trench isolation pattern ID sign 116 and the first interconnection pattern ID sign 117 are formed in this manner, which is the upper layer and which is the lower layer of which registration accuracy is to be detected can be readily determined by the registration mark 115.
FIG. 42 is a schematic plan view showing another example of the conventional registration mark 115. FIG. 43 is a schematic cross section of FIG. 42 taken along the line XLIII—XLIII, and FIG. 44 is a schematic cross section of FIG. 42 taken along the line XLIV—XLIV.
Referring to FIGS. 42 to 44, registration mark 115 basically has the same structure as the registration mark shown in FIGS. 39 to 41. It is noted, however, that in the registration mark 115 shown in FIGS. 42 to 44, the lower layer of which registration accuracy is to be detected is a layer including the first interconnection 103b formed on the main surface of a semiconductor substrate 119, and the upper layer is the layer including a second interconnection 105b formed on a first interlayer insulating film 108. Therefore, the first inspection pattern 103a that has a relatively large rectangular shape is formed by the same layer as the first interconnection 103b, while the second inspection pattern 105a of a relatively small rectangular shape is formed by the same layer as the second interconnection 105b. In registration mark 115, the first interconnection pattern ID sign 117 identifying the step of exposure to form the layer including the first interconnection 103b as the lower layer is formed by the first interconnection 103b, and the second interconnection pattern ID sign 136 identifying the step of exposure for forming the layer including the second interconnection 105b as the upper layer is formed by the second interconnection 105b. By using such a registration mark 115, it is possible to readily measure the registration accuracy between the layer including the first interconnection 103b and the layer including the second interconnection 105b. 
The registration mark 115 such as shown in FIGS. 39 to 44 is formed, for example, in inspection mark areas 129a to 133a, 130a, 131b, 130c and 131c of FIG. 38.
Using the registration mark 115 such as shown in FIGS. 39 to 44, at every step of exposure (one shot), an operation such as a measurement to confirm registration accuracy in that shot is carried out. At this time, when the steps of exposure is taken in order from chip areas 128c, 128a . . . using such a photomask 120 as shown in FIG. 37, it would be the case that the inspection mark area 129a in the shot to form chip area 128a is arranged next to the inspection mark area 130c in the shot to form chip area 128c, on one dicing line area 113, as shown in FIG. 45. Here, FIG. 45 is a schematic plan view of registration marks 115a-115c formed in inspection mark areas 129a and 130c of FIG. 38.
Referring to FIG. 45, in the dicing line area 113, inspection mark area 129a and inspection mark area 130c are arranged next to each other. In inspection mark area 129a, registration marks 115a and 115b to measure the registration accuracy in the step of exposure to form chip area 128a are arranged. In inspection mark area 130c, registration marks 115c and 115d to measure registration accuracy in the step of exposure to form chip area 128c are arranged.
Now, assume that the registration accuracy in the step of exposure to form chip area 128a is to be measured, for example. At this time, an operator specifies either one of registration marks 115a and 115b on the semiconductor substrate, and measures and takes data related to the registration accuracy using either one of registration marks 115a and 115b. When the registration marks 115c and 115d of the same shape are arranged next to each other on the same dicing line area 113 as shown in FIG. 45, it is possible that the operator erroneously measure the data related to registration marks 115c and 115d representing the registration accuracy in the step of exposure to form chip area 128c, instead of the registration marks 115a and 115b. In such a case, not the data of registration accuracy in the step of exposure to form chip area 128a but the data of registration accuracy in the step of exposure to form chip area 128c would be measured.
Therefore, when the data of registration accuracy in the step of exposure to form chip area 128a as an immediately preceding step of exposure is to be fed back to the step of exposure of the next shot area, for example, chip area 128b, erroneous data (data of registration accuracy of the step of exposure to form chip area 128c) would be fed back. Such a feed back of erroneous data deteriorates registration accuracy for the chip area 128b. 
In inspection mark areas 134a and 135b of FIG. 38, a testing element such as a TEG (Test Element Group) or a side monitor is formed. In inspection mark areas 134a and 135b, sometimes an electrode pad is formed to measure electric characteristic of the testing element. FIG. 46 shows an example of such an electrode pad. FIG. 46 is a schematic plan view of a pad group formed in inspection mark areas 134a and 135b. 
Referring to FIG. 46, in dicing line area 113, electrode pads 143 to measure electric characteristic of the testing element are formed in inspection mark areas 134a and 135a. Further, a pad 144 acting as an edge sensor is formed adjacent to electrode pad 143. Electrode pads 143 and pad 144 such as shown in FIG. 46 are formed in each of the inspection mark areas 134a and 135a shown in FIG. 38. Though electrode pads 143 formed in inspection mark areas 134a and 135a have similar appearances, types of testing elements to which the pads are connected differ dependent on the position. It is possible that types of testing elements differ in inspection mark areas 134a and 135a. In such a case, it is necessary to distinguish the electrode pad 143 formed in inspection mark area 134a from the electrode pad 143 formed in inspection mark area 135a. 
Conventionally, however, a mark to identify the electrode pad 143 for each of inspection mark areas 134a and 135a has not been specifically formed, as shown in FIG. 46. Therefore, there has been a possibility of an accident when electric characteristic is to be measured by connecting a probe to electrode pad 143 in inspection mark area 134a, that the operator measures the electrode pad 143 in inspection mark area 135a erroneously, taking data different from the necessary data.
In inspection mark areas 129a to 135a shown in FIG. 38, sometimes an isolated hole pattern 150 (Kelvin pattern) such as shown in FIG. 47 is formed, so as to enable process management inside the chip area 128a with higher accuracy. An operation of measuring the length of the isolated hole pattern 150 for process management, for example, is carried out. FIG. 47 is a schematic plan view showing a conventional isolated hole pattern formed in the inspection mark area of the semiconductor device. FIG. 48 is a schematic cross section of FIG. 47 taken along the line XLVIII—XLVIII.
Referring to FIGS. 47 and 48, in the area of inspection mark area where the isolated hole pattern 150 is formed, there is an active region 102 on the main surface of semiconductor substrate 119. A trench isolation insulating film 101 is arranged surrounding the active region 102. On the main surface of semiconductor substrate 119, the first interlayer insulating film 108 is formed. The second interconnection 105 is formed on the first interlayer insulating film 108. Isolated hole pattern 150 is formed by partially removing the first interlayer insulating film 108. A conductive film 149 is filled in the isolated hole pattern 150. The conductive film 149 connects the active region 102 to the second interconnection 105.
On the second interconnection 105, a second interlayer insulating film 109 is formed. On the second interlayer insulating film 109, third interconnections 107a to 107d are formed. By partially removing the second interlayer insulating film 109, a second contact hole 106 is formed. A conductive film 146 is filled in the second contact hole 106. The conductive film 146 connects the second interconnection 105 to the third interconnection 107. By partially removing the first and second interlayer insulating films 108 and 109, a second contact hole 106 is formed at a region positioned below the third interconnection 107c. In the second contact hole 106, a conductor 149 is filled. Conductor 149 connects active region 102 to the third interconnection 107c. 
When the length of such an isolated hole pattern 150 is to be measured, it is necessary for an operator to find the isolated hole pattern 150 on the semiconductor substrate. Actually, the size of the isolated hole pattern 150 is extremely small, and locating the isolated hole pattern 150 by the operator takes long time. Such an operation has been one of the causes of lower productivity in the steps of manufacturing the semiconductor device.
In inspection mark areas 129a to 135a shown in FIG. 38, in order to perform process management in chip area 128a with higher accuracy, a field effect transistor such as shown in FIG. 49, for example, may be formed as a testing element, and an operation of measuring the gate length, for example, may be performed. FIG. 49 is a schematic plan view showing the testing element formed in the inspection mark area of the conventional semiconductor device. FIG. 50 is a schematic cross section of FIG. 49 taken along the line L—L.
Referring to FIGS. 49 and 50, in the inspection mark area, active regions 102 which will be the source and drain regions are formed in the main surface of semiconductor substrate 119. The active region 102 is surrounded by a trench isolation insulating film 101. On the active region 102, a second interconnection 105 serving as a gate electrode is formed, with a gate insulating film (not shown) interposed. On the second interconnection 105, the first interlayer insulating film 108 is formed. At a region positioned above a prescribed region of active region 102, a second contact hole 106 is formed by partially removing the first interlayer insulating film 108. A conductive film 146 is filled in the second contact hole 106. Third interconnections 107b and 107c are formed to be connected to the conductive film 146, on the first interlayer insulating film 108. As can be seen from FIG. 49, the second interconnection 105 is electrically connected to the third interconnection 107a formed on the first interlayer insulating film 108, through the conductive film formed in contact hole 106. The active regions 102 as the source and drain regions, the gate insulating film (not shown) and the second interconnection 105 as the gate electrode constitute the field effect transistor as the testing element.
In the field effect transistor formed in this manner, the width of the second interconnection 105 serving as the gate electrode, that is, gate length L has been measured by using a scanning electron microscope (SEM). When the gate length L is to be measured, it is preferred that the measured value is calibrated, to improve measurement accuracy. Conventionally, however, there has been no such structure as to enable calibration of the measurement value.
In the testing element such as the field effect transistor shown in FIGS. 49 and 50, if a sign enabling identification of a process condition used to form the testing element or the process condition itself is indicated near the testing element, it becomes possible for the operator to measure the size of the testing element and, at the same time, to confirm the process condition. Therefore, when there is a failure in the step of photolithography, it is possible to recognize the occurrence of the failure easily and immediately. Conventionally, however, a mark representing data of the process condition in the step of photolithography to form the testing element has not particularly been provided.